DS283 april 7, 2009 www.xilinx.com 1 product specification ? 2009 xilinx, inc. xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise and other designate d brands included herein are trademarks of xilinx in the united states and other countries. all other trademarks are the property of their re spective owners. introduction the chipscope? plb iba core is a specialized bus ana- lyzer core designed to debug embedded systems that contain the ibm coreconnect processor local bus (plb). the chip- scope plb iba core in edk is based on tcl script that gen- erates a hdl wrapper to the plb iba and calls the chipscope core generator to generate the netlist based on user parameters. features ? multiple match units for trigger and data capture ? each match unit can be enabled and configured independently ? the match units for the plb iba are: ? plb control signals ? plb address units ? plb read data unit ? plb write data units ? plb master units (based on no. of masters) ? plb slave units (based on no. of slaves) ? generic trigger/data unit with selectable width ? for more information refer to the chipscope pro software and cores user guide in the chipscope installation for more information about the plb iba core, refer to the chipscope pro software and cores user guide . chipscope plb iba (bus analyzer) (v. 1.01a) DS283 april 7, 2009 product specification logicore? facts core specifics supported device family virtex?-4 version of core chipscope_plb_iba v1.01a resources used min max slices 219 411 luts 87 112 ffs 215 320 block rams 1 187 provided with core documentation product specification design file formats vhdl/edif constraints file n/a verification n/a instantiation template n/a reference designs none design tool requirements xilinx implementation tools ise? 11.1 or later verification chipscope pro 11.1 or later simulation not suppor ted in simulation
2 www.xilinx.com DS283 april 7, 2009 product specification functional description the chipscope opb iba core is a specialized bus analy zer core designed to deb ug embedded systems contain- ing the ibm coreconnect on-chip pr ocessor local bus (plb). the modul es and interconnects are shown in figure 1 . chipscope plb iba i/o signals the i/o signals for the chipscope plb iba are listed and described in table 1 . x-ref target - figure 1 figure 1: chipscope plb iba block diagram table 1: chipscope plb iba i/o signals signal name match unit interface i/o description chipscope_icon_control n/a n/a i[35:0] icon control signals iba_trig_in generic n/a i generic trigger inputs iba_trig_out generic n/a o iba trigger output plb_clk control mon_plb i plb clock plb_rst control mon_plb i plb reset plb_abort control mon_plb i plb abort bus request indicator plb_be control mon_plb i plb byte enable plb_buslock control mon_plb i plb bus lock plb_masterid control mon_plb i plb current master identifier plb_msize control mon_plb i plb da ta bus port width indicator plb_pavalid control mon_plb i plb pr imary address valid indicator plb_savalid control mon_plb i plb se condary address valid indicator plb_rdprim control mon_plb i plb sec ondary to primary read request indicator plb_wrprim control mon_plb plb sec ondary to primary write request indicator plb_rnw control mon_plb i plb read not write plb_size control mon_plb i plb transfer size plb_abus addr mon_plb i plb address bus plb_wrdbus wrdata mon_plb i plb write data bus chipscope icon icon_control clk plb mon_plb chipscope plb_iba iba_trig_in iba_trig_out DS283_01_092506
DS283 april 7, 2009 www.xilinx.com 3 product specification chipscope plb iba parameters to create a chipscope plb iba uniquely tailored for your system and to optimize perf ormance, specific features can be parameterized on the plb iba. table 2 describes the features that can be parameterized. for a detailed description of the plb iba core, see the chipscope pro software and cores user guide in the chipscope instal- lation. the chipscope plb iba peripheral supports multiple trigge r units that connect to the plb control bus, address bus, data bus, individual slave or master buses and a gene ric trigger input. each one of these trigger units can be enabled and parametrized independently. in the following table, c__unit refers to any one of these units and the parameters associated with the unit. the table also lists all the trigger units and the parameter names used to enable each of them. sl_rddbus rddata mon_plb i plb read data bus plb_maddrack master mon_plb i pl b master n a ddress acknowledge plb_mbusy master mon_plb i plb ma ster n slave busy indicator plb_merr master mon_plb i plb ma ster n slave error indicator plb_mrddack master mon_plb i plb ma ster n read data acknowledge plb_mrdwdaddr master mon_plb i plb master n read word address plb_mrearbitrate master mon_plb i plb master n bus rearbitrate indicator plb_mssize master mon_plb i plb ma ster n slave data bus port width plb_mwrdack master mon_plb i plb master n write data acknowledge m_abort master mon_plb i master n abort bus reque st indicator m_be master mon_plb i master n byte enables m_buslock master mon_ plb i master n bus lock m_msize master mon_plb i mast er n data bus port width m_priority master mon_plb i m aster n bus request priority m_request master mon_plb i master n bus request m_rnw master mon_plb i master n read not write m_size master mon_plb i master n transfer size sl_addrack slave mon_plb slave address acknowledge sl_rddack slave mon_plb slav e read data acknowledge sl_rdwdaddr slave mon_plb s lave read word address sl_rearbitrate slave mon_plb slave rearbitrate bus indicator sl_ssize slave mon_plb slave data bus port size indicator sl_wait slave mon_plb slave wait indicator sl_wrcomp slave mon_plb slave write transfer complete indicator sl_wrdack slave mon_plb slav e write data acknowledge table 1: chipscope plb iba i/o signals (cont?d) signal name match unit in terface i/o description
4 www.xilinx.com DS283 april 7, 2009 product specification . table 2: chipscope plb iba parameters feature / description parameter name allowable values default value vhdl type number of data samples captured for every trigger match c_num_data_samples integer (512*, 1024, 2048, 4096, 8192, 16384, 32768**, 65536**, 131072**) * except virtex-5 ** virtex-5 512 (1024 for virtex-5) integer enable the trigger out signal iba_trig_out which will be asserted when iba gets triggered c_enable_trigger_ out integer 1 = enable trigger out 0 = disable trigger out 1integer target family c_family xilinx fpga families virtex4 strings disable rpm placement information in netlist c_disable_rpm integer 1 = rpm disable 0 = rpm enabled in netlist 0integer disable srl16 usage c_d isable_srl16s integer 1 = disable 0 = enable 0integer trigger on rising or falling edge of clock c_rising_clock_ edge integer (1 = rising, 0 = falling) 1integer enable trigger sequencer in the ila c_enable_trigger_ sequencer integer 1 = enable 0 = disable 1integer maximum number of sequencer levels c_max_sequencer_ levels integer (1-16) 16 integer enable storage qualification for ila c_enable_storage_ qualification integer 1 = enable 0 = disable 1integer number of match units enabled for unit ex : plb control signals c__units ex : c_control_units integer (0-16) 0 = disable unit 1-16 = number of match units 0integer counter width for match unit ex : plb control signals match unit c__unit_ counter_width ex : c_control_unit_ counter_width integer (0-32) 0 - disable match counter 1-32 - match counter width (1) 0integer match tyoe for match unit ex : plb control signals match unit c__unit_ match_type ex : c_control_unit_ match_type "basic", "basic with edges", "extended", "extended with edges", "range", "range with edges" (1) "basic" (2) string plb control unit c_control_units integer (0-16) 1 integer plb address unit c_addr_units integer (0-16) 1 integer generic trigger unit c_generic_trigger_ units integer (0-16) 0 integer generic trigger input wi dth c_generic_trigger_ in_width integer (allowable range 1-1024 when generic trigger units are enabled) 0 (defaults to 8 when enabled) integer
DS283 april 7, 2009 www.xilinx.com 5 product specification allowable parameter combinations ? the parameter c_generic_trigger_in_width is valid only when the generic trigger input signal (not plb-bus related) is enabled on the chipscope plb iba by specifying the c_generic_trgger_units to be 1 or higher. ? parameters c__unit_counter_width an d c__unit_match_type are valid only when the corresponding trigger unit is enabled by setting c__units to be 1 or higher. ? the master and slave trigger units that can be enabled using c_master_units and c_slave_units is determined by the number of master or slave plb peripherals in the user?s processor design. refers to the position of a peri pheral on the plb bus (this is usually the same as the order in the user?s mhs design). for more information, refer to the chipscope pro software and cores user guide , in the chipscope installation. parameter - port dependencies design implementation design tools the chipscope plb iba design consists mainly of a tcl script. when the edk platgen tool is run, this tcl script gets called and the script internally calls the chipscop e pro core generator tool in commandline mode and pro- vides it an arguments file (.arg) to generate the chipsc ope plb iba netlist. the tcl script also generates a hdl wrapper to match the iba ports based on the core parameters. xst is the synthesis tool used for synthesizing the wrapper hdl generated for the chipscope plb iba. the edif netlist outputs from xst and chipscope core generato r are then input to the xilinx foundation tool suite for actual device implementation. target technology the intended target technology is all xilinx fpgas. plb write data unit c_wrdata_units integer (0-16) 0 integer plb read data unit c_rddata _units integer (0-16) 0 integer plb master (0-16) unit c_master_units integer (0-16) 0 integer plb slave (0-16) unit c_slave_units integer (0-16) 0 integer 1. refer to the chipscope pro software and cores user guide , in the chipscope installation 2. control : basic with edges; addr , trigger: extended with edges table 3: chipscope plb iba parame ter - port dependencies port name parameter de pendency description iba_trig_in c_generic_trigger_units c_generic_trigger_in_width the generic trigger input port a nd its width is determined by these two iba_trig_out c_enable_trigger_out the trig_out port is enabled when this parameter is set to 1 table 2: chipscope plb iba parameters (cont?d) feature / description parameter name allowable values default value vhdl type
6 www.xilinx.com DS283 april 7, 2009 product specification device utilization and performance benchmarks the device utilization varies widely based on the parameter combinations set by the user. restrictions maximum number of signals that can be monitored with a single iba is 256 signals. references ? more information on the chipscope pro so ftware and cores is available in the software and cores user guide , located at http://www.xilinx.com/documentation . ? information about hardware debugging using chipscope pro in edk is available in the platform studdio 11.1 online help, located at http://www.xilinx.com/documentation . ? information about hardware debugging using chipscope pro in system generator for dsp is available in the xilinx system generator for dsp user guide , located at http://www.xilinx.com/documentation . support xilinx provides technical support for this logicore product when used as described in the product documenta- tion. xilinx cannot guarantee timing, functionality, or suppor t of product if implemented in devices that are not defined in the documentation, if customized beyond that allowed in the product documentation, or if changes are made to any section of the design labeled do not modify . ordering information the plb iba core is provided under the ise design suite end-user lice nse agreement and can be generated using the xilinx embedded development kit (edk) system 11.1 or higher. edk is shipped with the xilinx ise design suite development software. revision history date version revision 01/16/2004 1.0 release 6.1i (initial xilinx release). 08/30/2004 1.1 release 6.3i. 10/31/2005 3.0 release 8.1i. 09/25/2006 4.0 release 9.1i. 12/10/2007 4.1 release 9.2i. 04/25/2008 5.0 release 10.1. 07/28/2008 5.1 release 10.1, service pack 2 changes. 04/07/2009 6.0 release 11.1.
DS283 april 7, 2009 www.xilinx.com 7 product specification notice of disclaimer xilinx is providing this design, code, or inform ation (collectively, the ?information?) to you ? as-is ? with no warranty of any kind, express or implied. xilinx makes no re presentation that the information, or any particular implementation thereof, is fre e from any claims of infringement. you are responsible for obtaining any rights you ma y require for any im plementation based on the information. all specifications are subject to change without notice. xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the information or any implementation based thereon, includi ng but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitnes s for a particular purpose. except as stated herein, none of the information may be copied, reproduced, distributed, republishe d, downloaded, displayed, posted, or transmitted in any form or by any mean s including, but not limited to, electr onic, mechanical, photocopying, recording, or otherwise, without the prio r written consent of xilinx.
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